This invention relates to micro-computing systems and the management of miniature self-contained processors with data storage capability assembled in arrays. The invention further relates to such arrays or lattices of miniature processors with the capability of providing a files-and-folders interface in a prevailing format to host equipment such as personal computers, personal digital assistants (PDA), global positioning systems (GPS), digital cameras, mobile telephones, appliances, instruments, vehicles, etc.
The use of multiple processors, prior to their miniaturization, has taken various paths. Logue, et al., in U.S. Pat. No. 4,268,908, show a modular microprocessor system with plural programmed logic arrays connected to a bus system for macro-processing. Each logic array executes a specific instruction beyond the standard set of instructions.
Hailpern, et al., in U.S. Pat. No. 4,881,164, use a plurality of microprocessors assembled in an array with each controlling a respective area of a large memory. Barker, et al., in U.S. Pat. No. 5,842,031 also use memory element processor arrays. These concepts have been expanded into single instruction multiple data (SIMD) architecture by Dieffenderfer, et al., in U.S. Pat. No. 5,822,608 and Meeker, et al., in U.S. Pat. No. 6,067,609.
With the advent of smaller non-volatile memory, such as non-volatile ROM and EEprom memory cells, pluralities of individual memory cells have been arranged in blocks to constitute an array. The circuit shown by Takashima, in U.S. Pat. No. 5,903,492, uses a microprocessor to perform processing; and has an input/output device with data storage connected to the microprocessor. The microprocessor is also connected to a semiconductor memory device including a plurality of memory cells each having a transistor gate and a ferroelectric capacitor.
Wallace, et al., in U.S. Pat. No. 5,867,417, uses computer memory cards densely packed with a large number of flash EEprom integrated circuit chips thereon. The Wallace computer memory system provides for the ability to removably connect one or more of such EEprom carrying memory cards, to a host computer system through a common controller circuit that interfaces between the memory cards and a standard computer bus. Wallace also can provide each card with its own individual controller circuitry, which then makes it connectable directly to the host computer system's standard bus, without the need for a common controller circuit interface unit.
Microprocessors have been assembled in lattice structures, and other such arrays, by Klingman, in U.S. Pat. No. 6,021,453, which shows an indefinitely extensible processor chain with self-propagation of code and data from the host computer end of the chain Klingman has assembled a general purpose microcomputer with an “upstream” bus and a “downstream” bus. Klingman's upstream bus interfaces an integrated multiport RAM that is shared between an upstream processor and a local (downstream) processor. Local (downstream) interrupts are associated with dedicated locations in RAM. Klingman proposes arrays of such processors under the control of the host computer, wherein an indefinitely long chain of such processors can be utilized by one host computer.
Rohlman, et al., U.S. application publication No. 20010032307, shows a microinstruction queue for an instruction pipeline within a microprocessor system. The pipeline has a plurality of units each with certain processing capabilities. At least one of the pipeline processing units can receive instructions from another pipeline processing unit, store the instructions and reissue at least some of the instructions after a “stall” occurs in the instruction pipeline.
Further, Nakano, in U.S. Pat. No. 6,021,511, shows a processor with a plurality of execution units integrated into a single chip. The execution unit has an initial failure signal output device and a separate operating failure detection device. These devices each provide a respective failure signal in the presence of such failure in that unit. Failure signals are monitored by an allocation controller, which allocates instructions only between non-failed units.
Clery, in U.S. Pat. No. 6,079,008, shows a parallel processing system processor with a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding buses. Clery uses a series of processing units to access his buses and to selectively execute his distributed instruction streams. His processing units individually may select and execute any instruction stream placed on a corresponding bus. These processing units autonomously execute conditional instructions, e.g., IF/ENDIF instructions, conditional looping instructions, etc. An enable flag within a processing unit is utilized to indicate the occurrence of conditions specified within a conditional instruction, and also to control the selective execution of instructions. An enable stack is utilized in the processing and execution of nested instructions.
These prior devices and systems, however, utilize multiple processors for such technical reasons as to increase the throughput of a centralized computing facility under control of system hardware and software. As will be demonstrated below, it is the object of the present invention rather to provide highly independent, self-contained, and concurrent processing and data storage in the form of a peripheral attachment to host devices in a miniature package while presenting to any host having a compatible external bus an image of a passive mass storage volume, configuration of such devices to be under control of end users.
Such passive memory devices include compact flash (CF) and other such passive memory devices, which are connected to host system buses through CF card adaptors, such as shown by Yotsutani in U.S. Pat. No. 6,109,931 and PCMCIA adaptors, such as shown by Moshayedi in U.S. Pat. No. 5,660,568. These CF devices have been connected individually such as shown by Tsai in U.S. Pat. No. 6,009,496, and into flash EEPROM memory system arrays. These arrays of passive memory devices have been connected to memory addressing controllers such as those shown by Harari et al, U.S. application publication No. 2001/0026472 A1 and US 2001/0002174 A1 or to controllers such as shown by Tobita in U.S. Pat. No. 6,275,436 B1. At times block memory addressing has been used as shown by Shinohara in U.S. Pat. No. 5,905,993,
These CF and other memory devices are completely passive, being without any active computing element (CPU), which CPU is capable of supporting an operating system or executing application programs within a self-contained miniature module. While as stated above, the prior art has contemplated distributed intelligence, it has not contemplated distributed intelligence masquerading as passive memory.
A second object of the present invention is to provide a miniature modular computing device for performing independent and concurrent computations, data storage, and input-output operations when attached to a host.
A third object of this invention is to provide this computing device with its own proprietary software and a self-contained operating system that enables it to operate as an intelligent media device, while presenting a passive virtual storage image to a host.
A further object of this invention is to provide this computing device where the projected look of a passive memory module effectively shares a virtual mass memory storage space within the device, while multiprogamming from that shared memory space concurrently with it being accessed from outside by a host.
A second further object of this invention is to provide lattice architecture for running proprietary operating system software permitting the interconnection of a plurality of these computing devices to operate as ultra-modular parallel processing units in relationship to one another and to have standardized interconnection hardware and software protocol to a host.
A third further object of this invention is to provide a secure and reliable means for packaging, delivering, and running proprietary software applications in a self-contained miniature module complete with a computing element (CPU), I/O circuits, an operating system, application program(s), and internally stored data.
A fourth further object of this invention is to provide a reliable and securable means for packaging and delivering and/or for collecting application-specific and/or private and/or proprietary data in such a way as to prevent unauthorized access, improper modification, and tampering via a self-contained miniature module complete with a computing element (CPU), non-volatile storage, I/O circuits, an operating system, application program(s), and internally stored data with minimal exposure to copying, tampering, software piracy, and other misuse.
A fifth further object of this invention is to provide a means for storing files and folders of computer data within a self-contained miniature module complete with a computing element (CPU), non-volatile storage, I/O circuits, an operating system, application program(s), and internally stored data wherein the said computing element and its software may continually monitor and/or scan said files and folders in said non-volatile storage to maintain the integrity of said data against damage, corruption, contamination, and the effects of computer viruses.
A sixth further object of this invention is to provide a means to substantially enhance the reliability of computer software applications by distributing and running said applications in highly independent, non-interfering modular units each having a self-contained miniature module complete with a computing element (CPU), non-volatile storage, I/O circuits, an operating system, application program(s), and internally stored data.
An even further object of this invention is to provide the proprietary operating system software for the lattice network of plural computing device with the ability to configure the computing devices in scalable and dynamically end-user re-configurable combinations of units forming a self-contained parallel processing and data storage system.